1. Field of the Invention
The present invention generally relates to an architecture and methodology in which the connectivity between cores, in a system-on-chip, can be verified to prevent connectivity errors, and help in verifying large designs.
2. Description of the Related Art
System-on-chip manufacturers receive system cores and integrate these system cores onto a chip. These system-on-chip manufacturers are concerned about the connections between the system cores and need a system and method to guarantee correct connectivity between the system cores.
As the capacities of integrated circuits continue to increase, more and more circuits are being integrated onto the same die. In the interest of time to market, larger numbers of logic cores are being used on the same die as well. Simple connectivity mistakes will become more likely given this growth in the size of system-on-chip designs.
The traditional solution to this problem is a thorough simulation of the chip at the top level. This solution becomes less feasible as chips grow larger due to an increase in complexity of function and exponential growth in the functional range to be simulated. For example, corner cases will be less likely to be hit in a reasonable amount of time.
IEEE specification 1149.1, otherwise known as Joint Test Action Group, has been used to check connectivity for chips on boards through scan chain structures. In this procedure, patterns are scanned into a chain on the outputs of a device, the signals are clocked into a scan chain on the inputs, and then the results are scanned out and compared against the input pattern. Similar concepts can be applied to on-chip cores. However, unique work must be done for each particular system-on-chip implementation to generate unique scan patterns.
Other conventional methodologies exist to check inter-core connections in processor-based system-on-chips. These conventional methodologies use specific, directed accesses over the processor-to-core interconnect to verify inter-core connectivity. This conventional methodology requires a large amount of simulation resources because the entire chip is being simulated. Further, this conventional methodology is not capable of checking every inter-core connection. Rather, only those inter-core connections that are within the processor interconnect hierarchy are checked.
Therefore, there exists a need to provide checking of all inter-core connections without requiring the testing of the entire chip functionality.
Further, there exists a need for minimizing the amount of simulation.
Additionally, a need exists for checking inter-core connectivity for any core interface in which two cores from a library are connected to one another.